Define and document the Design for Testability (DFT) architecture for multi-core System on Chips (SoCs), including strategies for hierarchical scan compression, MBIST (Memory BIST), Logic BIST and Analog Mixed Signal circuits.
Implement DFT logic, boundary scan, MBIST, scan chains, DFT compression, Clock Control block, and other DFT Internet Protocol (IP) blocks.
Work with the Register Transfer Level (RTL) and Physical Design (PD) team at SoC level, and with the subsystem DFT teams.
Write scripts to automate the DFT flow.
Develop tests that can be used for Production in the Automatic Test Equipment (ATE) flow.
Minimum qualifications:
Bachelor's degree in Science or Electrical or Electronics Engineering or a related technical field or equivalent practical experience.
5 years of experience with ATPG, Low Power designs, Built-In Self-Test (BIST), Joint Test Action Group (JTAG), Internal JTAG (IJTAG) tools and flow.
3 years of experience with SoC-level DFT architecture, implementation, and validation.
Experience with SoC DFT RTL implementation, RTL verification, Automatic Test Pattern Generation (ATPG)/MBIST/Boundary Scan (BSCAN)/Idd Quiescent Current (IDDQ) pattern generation.
Experience with DFT Embedded Deterministic Test (EDA) tool Tessent.
Preferred qualifications:
Experience in working on SoC-Level DFT.
Experience with Synthesis, Lint, Clock Domain Crossing (CDC), Logical Equivalence Check (LEC) and DFT timing and Static Timing Analysis (STA).
Experience with scripting languages such as Perl or Python.
Knowledge of performance design DFT techniques.
Knowledge of the end-to-end flows (e.g., Design, Verification, DFT and PD Phases) in a SOC cycle.
