Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios.
Create a constrained-random verification environment using SystemVerilog and the Universal Verification Methodology (UVM).
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Measure coverage to identify verification holes and to show progress towards tape-out.
Minimum qualifications:
Bachelor's degree in electrical engineering, computer science, a related field, or equivalent practical experience.
1 year of experience with verification methodology (e.g., Universal verification methodology (UVM)).
1 year of experience in the verification of IP designs (e.g., IP, SoC, vector CPUs).
Experience with SystemVerilog, SVA, and functional coverage.
Preferred qualifications:
Master's degree or PhD in electrical engineering, computer engineering, or computer science, with a focus on computer architecture.
2 years of experience with the full verification life cycle.
Experience in low-power design verification.
Experience developing and maintaining verification testbenches, test cases, and test environments.
Experience in artificial intelligence/machine learning (AI/ML) accelerators or vector processing units.
Experience with industry-standard simulators, revision control systems, and regression systems.
