Verify designs using verification techniques and methodologies.
Work cross-functionally to debug failures and verify the functional correctness of the design.
Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation is easy to use.
Minimum qualifications:
Bachelor's degree in electrical engineering, computer engineering, computer science, a related field, or equivalent practical experience.
4 years of experience with design verification (e.g., SystemVerilog/UVM).
Preferred qualifications:
Master's degree or PhD in electrical engineering, computer engineering, or computer science, with a focus on computer architecture.
Experience with interconnect protocols (e.g., AHB, AXI, ACE, CHI, CCIX, CXL).
Experience in one or more of the following: high speed protocols, memory management, caches hierarchies, coherency, DDR/LPDDR, PCIe, packet processors.
