Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).
Perform RTL coding, function/performance simulation debug, and Lint/Cyber Defense Center (CDC)/Formal Verification (FV)/
Unified Power Format (UPF) checks.
Participate in synthesis, timing/power closure, and FPGA/silicon bring-up.
Participate in test plan and coverage analysis of the block and ASIC-level verification.
Communicate and work with multi-disciplined and multi-site teams.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.
Preferred qualifications:
Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science.
Experience with a scripting language like Perl or Python.
Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT.
Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture.
Knowledge of memory compression, fabric, coherence, cache, or DRAM.
